Computer systems are often required to execute processing that exceeds the processing capability of a single processor. In addition, enhancement of processing capability required of a computer system tends to exceed enhancement of the capabilities possessed by a single processor.
For this reason, a memory-sharing multiprocessor which uses a plurality of CPUs that share memory space are coming into wider use in computer systems.
However, a memory-sharing multiprocessor is such that when it is attempted to maintain so-called cache coherence, namely the coherence between caches for the purpose of improving memory access performance processors, there are instances where other capabilities suffer. This tendency is particularly pronounced in large-scale multiprocessors. Accordingly, a first problem that arises in a memory-sharing multiprocessor is that the number of processors that share memory space cannot be increased without limit.
In order to solve this first problem, use is made of a multi-computer system in which a plurality of computers are interconnected by a switched network in the form of a large-scale numerical arithmetic unit used in research applications, etc., thereby making it unnecessary for memory space to be shared by these computers. There are increasing opportunities to utilize multi-computer systems, which are obtained by such networking of multiple computers that do not guarantee cache coherence, even in ordinary computer systems.
In such a multi-computer system, however, it is necessary for data that has been processed by each of the plurality of computers to be transferred to another computer. When the amount of data increases, therefore, a second problem which arises is an increase in the time expended in the data processing processors for the purpose of transferring data between computers, as a result of which the overall processing capability of the multi-computer system declines.
In order to solve the second problem, a system has been developed in which a transfer device dedicated solely to data transfer is incorporated in each computer of the multi-computer system and data transfer is performed by the transfer device in units larger than the data size processed at one time by the processor. This improves transfer capability, shortens the time needed by the processor to perform the data transfer and enhances the overall performance of a multiple-host apparatus.
Though operating systems have been started out by being small and simple, recent operating systems, however, are large in scale and of great complexity. A third problem, which relates to a switching from a user process to an operating-system process (OS process), is that it is not possible to ignore the overhead of context switches for making this transition between processes when relying upon the above-described data transfer.
In order to solve the third problem, a system has been developed in which transfer-source/transfer-destination addresses at the time of data transfer are specified by virtual addresses in the address space of the user process, with a virtual address being translated to a real address by the above-mentioned transfer device.
In accordance with this system, the need to rely upon the operating system to translate a virtual address to a real address whenever a data transfer is designated can be eliminated, as a result of which it is possible to reduce the frequency of context switching.
The transfer device has an address translation function that holds translation information which is for translating a virtual address to a physical address. However, since the overall translation information of virtual addresses is very large, a fourth problem which arises is that it is difficult for the transfer device to be equipped internally with an address translation table that holds the entirety of the translation information relating to the virtual addresses.
In order to solve the fourth problem, a method in wide use places the address translation table, which holds the entirety of the translation information of the virtual addresses, external to the transfer device, and internally provides the transfer device with a small address translation table, i.e., a TLB (Translation Look-aside Buffer), that holds only the translation information from the address translation table that corresponds to some of the virtual addresses used most recently.